Conventionally, an operational amplifier (op-amp) is used for accurate charge transfer in switched capacitor circuits. The op-amp has differential inputs and an output. In operation, the op-amp senses the voltage difference at the differential inputs, and drives an output node continuously with its output to achieve a virtual ground condition at the differential inputs. As long as high-gain and wide-bandwidth op-amps are available this method is accurate and robust. However, it is relatively difficult to make power efficient, high-gain, and wide-bandwidth op-amps in nano-scale complementary metal oxide semiconductor (CMOS) technology.
A related art zero-crossing based circuit technique replaces the op-amp with a zero-crossing detector and a current source. FIG. 1A is a schematic of an exemplary related art zero-crossing detector based circuit 10. The circuit 10 includes a zero-crossing detector ZCD1 and a current source 12 that supplies a current I1. The circuit 10 also includes switches S1, S2, S3, S4, S5, S6, and S7 along with capacitors C1, C2, and C3. A switch controller (not shown) controls the opening and closing of switches S1 through S6. The switch S7 is opened and closed in response to the output state of the zero-crossing detector ZCD1.
FIG. 1B is a series of graphs depicting switching phases φ1, φ2, φp, and φ2e, along with an output voltage Vout, and a virtual ground node voltage VX for the circuit 10 (FIG. 1A). In operation, the circuit 10 samples an input signal (Vin) that is applied to the capacitor C1 by closing switches S1 and S3. Switches S2 and S4 are open during this sampling period. This sampling step is similar to a sampling step used in the operation of traditional op-amp based switched capacitor circuits. Optionally, the switch S6 may be closed during the sampling period to ensure that the output voltage Vout is at ground potential (GND). After the sampling period, the capacitor C1 and the second capacitor C2 are selectably coupled to a virtual ground node 14 that includes an input of the zero-crossing detector ZCD1 by closing the switches S2 and S4. As a result, a charge accumulated by the capacitor C1 from Vin is transferred to the second capacitor C2. The charge transfer starts in response to the preset phase φp, which initializes the output voltage Vout to GND via the switch S6. After the preset phase φp concludes, the current source 12 begins charging the output capacitor C3 with the current I1. The zero-crossing detector ZCD1 monitors the virtual ground node 14, while the current I1 is charging the output capacitor C3. The zero-crossing detector ZCD1 detects the instant of the zero-crossing of the virtual ground node voltage Vx, and opens the switch S7 coupled to a terminal node 16. As such, the voltage Vout and the virtual ground node voltage Vx increase linearly in time and stop once a virtual ground condition Vcm (common mode voltage) is met. The circuit 10 is power efficient because the zero-crossing detector ZCD1 is significantly more power efficient than a high-gain wide-bandwidth op-amp typically used in circuits having the same function as circuit 10. Moreover, the circuit 10 eliminates stability issues, due to semi-open loop operation.
FIG. 2A is a schematic of a modified version of the related art zero-crossing detector circuit 10 of FIG. 1A having a reversed direction current source. For example, charge transfer operations of zero-crossing based circuits can be done in an opposite direction of the current source 10 shown in FIG. 1A. A configuration for an opposite output charging direction is depicted in FIG. 2A. In this case, the output voltage Vout is initialized to a supply voltage VDD instead of GND during the preset phase (φp) by the preset switch S6. In this configuration the preset switch S6 is coupled between a source of the supply voltage VDD and a node between the switch S5 and a first terminal of the capacitor C3. In operation, the zero-crossing detector ZCD1 monitors the zero crossing at the input of the zero-crossing detector ZCD1 while the current source 12 discharges the output voltage Vout via the current I1. FIG. 2B shows a similar operation to FIG. 1B except that the direction of change for the output voltage Vout and the virtual ground node voltage Vx are reversed with those shown in FIG. 1B. It may be necessary to switch the two inputs of the zero-crossing detector ZCD1 in cases where a same version of zero-crossing detector ZCD1 is reused in circuit 10 of FIG. 2A.
For the following discussion FIG. 3A is a schematic reproduction of the related art zero-crossing detector circuit of FIG. 1. The operation aspects of the circuit 10 of FIG. 1A and FIG. 2A are described as ideal operations. In practical terms, the response time between a zero-crossing detection and an output change of the zero-crossing detector 10 and a corresponding switch transition for the switch S7 is not instantaneous. Instead, there is a finite delay (td) in turning off the switch S7 after a zero-crossing at the input of the zero-crossing detector ZCD1.
FIG. 3B is a series of graphs depicting switching phases φ1, φ2, φp, and φ2e, along with an output voltage Vout, a virtual ground node voltage VX and an offset caused by the delay td of the circuit 10 of FIG. 3A. Due to the delay td, the virtual ground node voltage Vx overshoots an ideal voltage by a voltage overshoot Vxover given by
                                          V            xover                    =                                    t              d                        ·                                          ⅆ                                  V                  x                                                            ⅆ                t                                                    ,                            (        1        )            which leads to an offset voltage Voffset in the output voltage Vout. The voltage offset Voffset is given by
                              V          offset                =                              t            d                    ·                                                    ⅆ                Vout                                            ⅆ                t                                      .                                              (        2        )            Therefore, a final output voltage Vfinal is given byVfinal=Vsignal+Voffset,  (3)wherein the signal voltage Vsignal equals an ideal output voltage.
Related art techniques address the inaccuracy due to the virtual ground node voltage Vx overshoot and the resulting offset voltage Voffset by implementing a coarse charge transfer phase followed by a fine charge transfer phase. The goal of this dual phase charge transfer is to reduce the ramp rate right before the zero-crossing detector ZCD1 detects a zero-crossing. In this regard and as shown in FIG. 4A, one related art modification adds a current control 18.
As shown in FIG. 4B, a charge transfer begins with a coarse charging phase (φc), wherein the current source 12 in response to the current control 18 charges the capacitor C3 relatively quickly via a relatively high current ramp of the current I1. While the current source 12 charges the capacitor C3, the zero-crossing detector ZCD1 detects when the virtual ground node voltage Vx reaches a predetermined voltage level Vclose that is relatively close to the virtual ground condition Vcm. Once the virtual ground node voltage Vx reaches the predetermined voltage level Vclose, the current control 18 significantly reduces the relatively high current ramp of the current I1, thereby replacing the coarse charging phase φc with a fine charging phase φf. The resulting offset voltage Voffset is relatively lower, which results in a relatively greater accuracy of charge transfer to the capacitor C2 and higher accuracy of the output voltage on the capacitor C3. The fine charging phase ends when the virtual ground node voltage Vx crosses the virtual ground condition Vcm. The charge accumulated by the capacitor C3 is sampled by a following sampling stage (not shown). While the modified circuit 10 of FIG. 4 provides improved accuracy, a small but significant error in the output voltage Vout remains due to the smaller but still significant offset voltage Voffset.
Additional related art techniques to compensate for the offset voltage Voffset include employing a programmable offset in the zero-crossing detector ZCD1 and/or coupling a small capacitor array (not shown) to the virtual ground node 14 to cancel the offset voltage Voffset. However, after considering temperature and process variations, these related art techniques are relatively impractical. What is needed is a level-crossing based circuit and method that provides cancellation of offset voltage and tracking of the offset variation with efficiencies in power consumption and die area.